DocumentCode :
2559747
Title :
A 2.5 14-bit 180-mW Cascaded ΣΔ ADC for ADSL2+ Applications
Author :
Chang, Teng-Hung ; Dung, Lan-Rong ; Guo, Jwin-Yen ; Yang, Kai-Jiun
Author_Institution :
National Chaio Tung University, Taiwan. Email: thchang.ece91g@nctu.edu.tw
fYear :
2006
fDate :
13-15 Nov. 2006
Firstpage :
59
Lastpage :
62
Abstract :
This paper presents a sigma-delta (ΣΔ) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application (ADSL2+). The core of the ADC is a cascaded 2-1-1 ΣΔ modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2 MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio (SNDR) of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-μm CMOS technology, in a 2.4-mm2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.
Keywords :
CMOS integrated circuits; delta-sigma modulation; digital subscriber lines; ΣΔ modulator; ADSL2+ applications; CMOS technology; analog-to-digital converter; bandwidth 2.2 MHz; cascaded ΣΔ ADC; decimation filter; extended bandwidth asymmetric digital subscriber line application; noise figure 78 dB; noise figure 86 dB; power 180 mW; reference voltage buffers; resonator-based topology; size 0.25 μm; tri-level quantizers; voltage 2.5 V; Analog-digital conversion; Bandwidth; CMOS technology; DSL; Delta-sigma modulation; Distortion; Dynamic range; Filters; Topology; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
Conference_Location :
Hangzhou
Print_ISBN :
0-7803-9734-7
Electronic_ISBN :
0-7803-97375-5
Type :
conf
DOI :
10.1109/ASSCC.2006.357851
Filename :
4197590
Link To Document :
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