An Inverter Based 2-MHz 42-μW ΔΣ ADC with 20-KHz Bandwidth and 66dB Dynamic Range

Author

Su, Chauchin ; Lin, Po-Chen ; Lu, Hungwen

Author_Institution

Nat. Chiao Tung Univ., Hsin-Chu

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

63

Lastpage

66

Abstract

This paper presented an inverter based 3^rd order sigma-delta ADC. Cascode structure and auto-zeroing mechanism are proposed for the gain enhancement and offset cancellation. The ADC has been implemented in TSMC 2P6M 0.18 μm CMOS technology with a core area of 0.54 mm². The measurement results show that for the 1-V supply, 20-KHz bandwidth, and 2-MHz sampling rate, the power consumption is 42 μW and the dynamic range of 66.02 dB.

Keywords

CMOS integrated circuits; invertors; sigma-delta modulation; 3rd order sigma delta ADC; CMOS technology; Cascode structure; TSMC; auto zeroing mechanism; bandwidth 20 kHz; dynamic range; frequency 2 MHz; gain enhancement; inverter; measurement results; offset cancellation; power 42 μW; power consumption; size 0.18 μm; voltage 1 V; Bandwidth; CMOS technology; Circuit stability; Delta-sigma modulation; Dynamic range; Energy consumption; Inverters; Multi-stage noise shaping; Signal to noise ratio; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357852

Filename

4197591