Title :
Effective march algorithms for testing single-order addressed memories
Author :
van de Goor, A.J. ; Zorian, Yervant
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
The testing problems for the single-order addressed (SOA) memory, are discussed and a family of test algorithms for it are presented. SOA memories are used in various applications, such as FIFOs, where the sequence of addressing need to be in a certain order, more specifically in a single-order (e.g., from address 0 to n-1). Consequently this restricted addressing capability allows faster address generation, and hence shorter overall access time. The existing march test algorithms, which are developed to test random-access memories, cannot be adopted by the users of SOA memories, due to the fact that all these algorithms march through the memory in two directions; whereas SOA memories are limited in terms of address order to a single direction. However, the existing march tests provide a basis for a new family of algorithms targeting SOA memories. These algorithms can be used as externally applied tests or can be implemented as BIST hardware
Keywords :
automatic test software; built-in self test; circuit analysis computing; integrated circuit testing; random-access storage; BIST hardware; addressing faults; coupling faults; effective march algorithms; externally applied tests; fault models; stuck-at faults; testing single-order addressed memories; transition faults; Automatic testing; CADCAM; Circuit testing; Computer aided manufacturing; Decoding; Logic arrays; Random access memory; Read-write memory; Registers; Semiconductor optical amplifiers;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386425
