DocumentCode :
2559834
Title :
Strategies for development and modelling of VHDL based macrocell library
Author :
Nousiainen, Juha ; Nummela, Arto ; Nurmi, Jari ; Tenhunen, Hannu
Author_Institution :
Signal Process. Lab., Tampere Univ. of Technol., Finland
fYear :
1993
fDate :
22-25 Feb 1993
Firstpage :
478
Lastpage :
482
Abstract :
Digital Signal Processing (DSP) applications are suitable for automated library based high-level design. Strategies to generate technology independent DSP macrocell library using VHDL and its interfaced tools, are discussed with some practical examples. The main focus is in the modeling strategies and framework of the DSP macrocell library
Keywords :
application specific integrated circuits; cellular arrays; digital signal processing chips; hardware description languages; high level synthesis; logic arrays; DSP macrocell library; DSP-ASIC design; VHDL based macrocell library; automated library based high-level design; modeling strategies; Algorithm design and analysis; Design optimization; Digital signal processing; Macrocell networks; Process design; Signal design; Signal processing algorithms; Silicon; Software libraries; Software tools;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
Type :
conf
DOI :
10.1109/EDAC.1993.386429
Filename :
386429
Link To Document :
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