DocumentCode :
2559873
Title :
A process-insensitive current-controlled delay generator with threshold voltage compensation
Author :
Wei, He-Gong ; Chio, U-Fat ; Sin, Sai-Weng ; Seng-Pan, U. ; Martins, R.P.
Author_Institution :
Analog & Mixed Signal VLSI Lab., Univ. of Macau, Macao, China
fYear :
2010
fDate :
8-10 Nov. 2010
Firstpage :
1
Lastpage :
4
Abstract :
A process-insensitive current-controlled delay generator is presented with a large tunable range of the time delay. By adopting process variation compensation techniques in the generation of time delay, the delay generator is able to provide process-insensitive clock pulses. The circuit has been fabricated in 90 nm CMOS technology, consumes 310 μW from a 1.1V supply. Using, in a typical case, 20μA of reference current, it can generate a delay of 2.36 ns. The delay variation observed in 14 measured chips has shown a standard deviation of 1.24%.
Keywords :
CMOS integrated circuits; clocks; compensation; delay circuits; logic circuits; CMOS technology; current 20 muA; inverter; power 310 muW; process variation compensation techniques; process-insensitive clock pulses; process-insensitive current-controlled delay generator; size 90 nm; threshold voltage compensation; time 2.36 ns; time delay generation; voltage 1.1 V; Clocks; Current measurement; Delay; Delay effects; Generators; Inverters; Oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
Type :
conf
DOI :
10.1109/ASSCC.2010.5716595
Filename :
5716595
Link To Document :
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