DocumentCode
2559889
Title
A Phase-to-Digital Converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3 V
Author
Hayashi, Isamu ; Matsubara, Takeshi ; Kumaki, Satoshi ; Johari, Abul Hasan ; Ishikuro, Hiroki ; Kuroda, Tadahiro
Author_Institution
Extremely Low Power R&D Dept, STARC, Tokyo, Japan
fYear
2010
fDate
8-10 Nov. 2010
Firstpage
1
Lastpage
4
Abstract
A Phase-to-Digital Converter (PDC), - an improved scheme of Time-to-Digital Converter (TDC) -, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).
Keywords
calibration; convertors; digital phase locked loops; oscillators; PVT tolerant ADPLL; all digital PLL; body-bias controlled vernier TDC; calibration; digital controlled coupled oscillator; phase-to-digital converter; time-to-digital converter; voltage 0.3 V; wide tuning range; Calibration; Clocks; Converters; Delay; Oscillators; Power demand;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location
Beijing
Print_ISBN
978-1-4244-8300-6
Type
conf
DOI
10.1109/ASSCC.2010.5716596
Filename
5716596
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