A skew assumption logic simulation technique for potential spike detection

A simulation technique that a set of signal transitions which may cause the simulated circuit to exhibit incorrect behavior by assuming event skew is described. Incorporation of timing check primitive enables detailed timing error messages composed of the past signal transitions at the primary inputs which cause the error, the internal gate which generates the potential spike signal and the internal signal transitions related to the error. The logic simulator on which the novel simulation technique is installed helps designers to find hazardous designs in the circuit under verification. LSIs verified by using the simulator are free from timing skew troubles on the bench of ATE (Automatic Test Equipment)