Title :
A new method of identifying critical paths for performance optimization
Author :
Huang, Shiang-Tang ; Parng, Tai-Ming ; Shyu, Jyuo-Min
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
It is shown that during performance optimization some false paths may become sensitizable and that the selection of critical paths needs to consider some false paths besides sensitizable paths. These critical paths are called candidate paths. Techniques for extracting candidate paths, and an effective graph model for representing and manipulating the huge number of candidate paths have been developed. The speed and memory utilization of the proposed method are demonstrated using ISCAS benchmark circuits
Keywords :
circuit analysis computing; circuit optimisation; critical path analysis; logic CAD; timing; ISCAS benchmark circuits; candidate paths; critical paths; effective graph model; false paths; path identification method; performance optimization; sensitizable paths; timing analysis; Central Processing Unit; Circuit topology; Cost function; Councils; Delay effects; Logic; Optimization; Performance analysis; Timing;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386433
