• DocumentCode
    2559924
  • Title

    A Parallel Carrier Synchronization Algorithm for High-Speed Digital Communication Systems

  • Author

    Liu, Ce-Lun ; Bu, Xiang-yuan ; An, Jian-ping

  • Author_Institution
    Dept. of Inf. & Electron., Beijing Inst. of Technol., Beijing, China
  • fYear
    2010
  • fDate
    23-25 Sept. 2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    For high-speed digital receivers, the crucial problem is to find a parallel carrier synchronization algorithm, but the traditional carrier synchronization methods based on phase-locked loop (PLL) are difficult to be parallel implemented. In this paper, we propose a parallelizable carrier synchronization algorithm based on maximum likelihood estimation (MLE). The simulation results show that the performances of locking and without losing are very good when proper data length for estimation is selected. Finally, the algorithm is applied to practical communication systems and the results show that the device utilization and BER performance loss are all very low.
  • Keywords
    computational complexity; digital communication; maximum likelihood estimation; parallel algorithms; phase locked loops; phase shift keying; receivers; synchronisation; BER performance loss; MLE; MPSK modulated high-speed communication system; PLL; computational complexity; high-speed digital communication systems; high-speed digital receivers; maximum likelihood estimation; parallel carrier synchronization algorithm; phase-locked loop; Computational complexity; Maximum likelihood estimation; Modulation; Receivers; Signal processing algorithms; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wireless Communications Networking and Mobile Computing (WiCOM), 2010 6th International Conference on
  • Conference_Location
    Chengdu
  • Print_ISBN
    978-1-4244-3708-5
  • Electronic_ISBN
    978-1-4244-3709-2
  • Type

    conf

  • DOI
    10.1109/WICOM.2010.5600952
  • Filename
    5600952