Title :
A new accurate and hierarchical timing analysis approach
Author :
Blaquiere, Yves ; Dagenais, Michel ; Savaria, Yvon
Author_Institution :
Dept. of Math. & Comput. Sci., Univ. du Quebec, Montreal, Que., Canada
Abstract :
A new and efficient procedure to evaluate the timing performance of VLSI circuits with circuit level accuracy is proposed. The efficiency is obtained by rapidly identifying the critical portions of the circuit at high hierarchical levels with rough delay models. These portions are then successively studied at more detailed levels for maximal accuracy. This procedure, implemented and applied to several circuits, is shown to significantly reduce the analysis time
Keywords :
VLSI; circuit analysis computing; logic CAD; timing; VLSI circuits; circuit level accuracy; hierarchical timing analysis; timing performance; Circuit analysis; Circuit analysis computing; Computational modeling; Computer science; Delay; Mathematics; Performance analysis; Switches; Timing; Very large scale integration;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386434
