CHAN: An efficient critical path analysis algorithm

Author

Chang, Hoon ; Abraham, Jacob A.

Author_Institution

Comput. Eng. Res. Center, Univ. of Texas, Austin, TX, USA

fYear

1993

fDate

22-25 Feb 1993

Firstpage

444

Lastpage

448

Abstract

An efficient critical path analysis algorithm (CHAN) based on the automatic test pattern generation (ATPG) method PODEM is presented. The approach does not require generation of the path list and elimination of false paths, and the critical path of the circuit is found accurately. In CHAN, the limitations of conventional approaches are overcome, and the critical path is detected in vastly improved times in most cases considered

Keywords

VLSI; circuit CAD; circuit analysis computing; critical path analysis; integrated circuit design; logic CAD; logic testing; timing; CHAN; PODEM; VLSI circuits; automatic test pattern generation; efficient critical path analysis algorithm; timing verification; Algorithm design and analysis; Automatic test pattern generation; Circuit analysis; Circuit testing; Clocks; Delay estimation; Jacobian matrices; SPICE; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Conference_Location

Paris

Print_ISBN

0-8186-3410-3

Type

conf

DOI

10.1109/EDAC.1993.386435

Filename

386435

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2559937