DocumentCode :
2560011
Title :
Circuit delay optimization as a multiple choice linear knapsack program
Author :
Karkowski, I.
Author_Institution :
Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
fYear :
1993
fDate :
22-25 Feb 1993
Firstpage :
419
Lastpage :
423
Abstract :
An efficient way for optimizing timing under constraints as an integer programming problem is presented. Actually, a surrogate dual of a mathematical programming problem is solved within global enumeration schemes. The kernel of each iteration is nothing else than an instance of the multiple choice linear knapsack problem, for which a O( n) algorithm exists. Arbitrary, discrete cost-delay functions for modeling circuits, which are especially suitable for Sea of Gates designs are used. Experiments confirm usefulness of this approach
Keywords :
circuit layout CAD; circuit optimisation; delays; integer programming; integrated circuit modelling; logic CAD; logic arrays; timing; Sea of Gates designs; chip layout design; circuit delay optimisation; discrete cost-delay functions; global enumeration schemes; integer programming problem; multiple choice linear knapsack program; timing under constraints; Circuits; Delay; Ear; Flip-flops; Kernel; Linear programming; Pins; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
Type :
conf
DOI :
10.1109/EDAC.1993.386439
Filename :
386439
Link To Document :
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