Results of analyzing VLSI interconnect structures by a methodology based on mixed frequency-time domain

Author

Perdomo, Salvador ; Nunez, Antonio

Author_Institution

Center for Applied Microelectron., Univ. of Las Palmas de Gran Canaria, Spain

fYear

1993

fDate

22-25 Feb 1993

Firstpage

409

Lastpage

413

Abstract

The results of the analysis, from a digital point of view, of some interconnection structures in GaAs integrated circuits are presented. These results are given in graphical format, as engineering charts, to assist designers, and with a polynomial fitting useful for timing analysis. In addition to computing timing parameters such as propagation time and signed slopes (waveforms), the methodology also provides estimations of noise and crosstalk levels

Keywords

circuit layout CAD; digital integrated circuits; integrated circuit interconnections; integrated circuit layout; polynomials; time-frequency analysis; timing; very high speed integrated circuits; GaAs; III-V semiconductor IC; VLSI interconnect structures; crosstalk levels; engineering charts; layout design; mixed frequency-time domain; noise; polynomial fitting; propagation time; signed slopes; timing analysis; very high speed circuits; waveforms; Crosstalk; Design engineering; Digital integrated circuits; Fitting; Gallium arsenide; Integrated circuit interconnections; Integrated circuit noise; Polynomials; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Conference_Location

Paris

Print_ISBN

0-8186-3410-3

Type

conf

DOI

10.1109/EDAC.1993.386441

Filename

386441