A modified in-cell ADC using ranked order extraction

Author

Vesalainen, Laura ; Poikonen, Jonne ; Paasio, Ari

Author_Institution

Lab. of Microelectron., Turku Univ., Finland

fYear

2005

fDate

28-30 May 2005

Firstpage

23

Lastpage

26

Abstract

For adopting a mixed-mode approach for an array processor implementation, the reuse of analog components is one of the main motivations. This paper describes a modification of a previously presented ADC, in which the two most significant bits of the conversion are generated with the help of a ranked order filter and some additional logic. This strategy saves area in the ADC by efficient reuse of the large analog transistors of the ranked order filter. The converter structure along with simulations in a 0.18 μm digital CMOS technology are shown.

Keywords

CMOS integrated circuits; analogue-digital conversion; arrays; circuit simulation; filters; mixed analogue-digital integrated circuits; transistors; 0.18 micron; analog component reuse; large analog transistor reuse; mixed-mode array processor; modified in-cell ADC; ranked order extraction; ranked order filter; CMOS logic circuits; CMOS technology; Computer science; Concurrent computing; Filters; Laboratories; Microelectronics; Silicon; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Cellular Neural Networks and Their Applications, 2005 9th International Workshop on

Print_ISBN

0-7803-9185-3

Type

conf

DOI

10.1109/CNNA.2005.1543151

Filename

1543151