• DocumentCode
    2560120
  • Title

    Coherent optimization strategies for multilevel synthesis

  • Author

    Sakouti, K. ; Abouzeid, P. ; Belrhiti, M. ; Crastes, M. ; Saucier, G.

  • Author_Institution
    Inst. Nat. Polytech. de Grenoble, France
  • fYear
    1993
  • fDate
    22-25 Feb 1993
  • Firstpage
    378
  • Lastpage
    385
  • Abstract
    It is shown that coherent optimization strategies for multilevel synthesis should rely on a good link between the factorization, the technology mapping and the netlist optimization. Factorization options are shown to play a key role. The technology mapping should optimize both area and critical path and only netlist structure preserving optimization techniques (buffer insertion, gate replication) should be applied first. Only in a last step resynthesis of critical areas based on a local view is applied. The approach has been experimented on set of large combinational benchmarks
  • Keywords
    circuit optimisation; combinational circuits; logic CAD; logic gates; logic partitioning; multivalued logic circuits; buffer insertion; coherent optimization strategies; factorization; gate replication; large combinational benchmarks; multilevel synthesis; netlist optimization; technology mapping; Boolean functions; Logic; Optimization methods; Process design; Timing; Vegetation mapping;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
  • Conference_Location
    Paris
  • Print_ISBN
    0-8186-3410-3
  • Type

    conf

  • DOI
    10.1109/EDAC.1993.386446
  • Filename
    386446