Circuit activity driven multilevel logic optimization for low power reliable operation

The problem of optimization of multilevel combinational logic to achieve low power dissipation as well as low area is considered wherein it is assumed that static CMOS gates are used. Given a multilevel Boolean network as a collection of functions, the system determines a new function at a time, adds it to the collection and expresses the existing functions in terms of it. In selecting the new function the effect on power dissipation as well as area are considered. The authors describe an efficient implementation of a general algorithm to compute expected number of transitions per unit time at circuit nodes. These numbers are in turn used to compute power dissipation. A prototype multilevel logic optimization system has been implemented. Results are given for a selection of benchmark examples