Title :
Clocked comparator for high-speed applications in 65nm technology
Author :
Abbas, Mohamed ; Furukawa, Yasuo ; Komatsu, Satoshi ; Takahiro, J.Y. ; Asada, Kunihiro
Author_Institution :
VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan
Abstract :
This paper presents a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. Also, the paper presents a new cost effective technique for measuring the maximum speed of the clocked comparator. The measurement and simulation results show that the proposed design has an average of 31% higher speed and ~17% less active area than the conventional design.
Keywords :
CMOS integrated circuits; comparators (circuits); delays; integrated circuit design; CMOS technology; MOS transistors; high frequency signal digitization; on-chip high-speed clocked comparator; size 65 nm; CMOS integrated circuits; Clocks; Delay; Frequency measurement; Integrated circuit modeling; Semiconductor device measurement; System-on-a-chip;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716609
