DocumentCode :
2560174
Title :
A novel approach to cost-effective estimate of power dissipation in CMOS ICs
Author :
Benini, L. ; Favalli, M. ; Olivo, P. ; Ricco, Bruno
Author_Institution :
DEIS Univ. di Bologna, Italy
fYear :
1993
fDate :
22-25 Feb 1993
Firstpage :
354
Lastpage :
360
Abstract :
An approach to the estimate of power dissipation in CMOS ICs based on the current limited model of MOS transistors able to accurately evaluate current waveforms for all types of digital circuits is presented. The efficiency of the tool developed is such that ICs with up to 104-105 transistors can be cost-effectively treated without any need of arbitrary partitioning. In addition, the algorithm can be used to study problems related to excessive values of supply currents, such as electromigration or noise, and voltage drops on power buses. Results obtained with significant benchmarks are shown in order to demonstrate the accuracy and the efficiency of the proposed method
Keywords :
CMOS logic circuits; circuit analysis computing; integrated circuit modelling; logic CAD; waveform analysis; CMOS ICs; MOS transistors; algorithm; combinational logic; cost-effective estimate; current limited model; current waveforms; digital circuits; electromigration; excessive values; logic circuits; noise; power buses; power dissipation; sequential logic; supply currents; voltage drops; CMOS digital integrated circuits; CMOS logic circuits; Circuit noise; Circuit simulation; Circuit testing; Condition monitoring; Logic testing; Power dissipation; Semiconductor device modeling; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
Type :
conf
DOI :
10.1109/EDAC.1993.386450
Filename :
386450
Link To Document :
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