DocumentCode
2560183
Title
A 120-GHz transmitter and receiver chipset with 9-Gbps data rate using 65-nm CMOS technology
Author
Fujimoto, Ryuichi ; Motoyoshi, Mizuki ; Yodprasit, Uroschanit ; Takano, Kyoya ; Fujishima, Minoru
Author_Institution
ELP R&D Dept., Semicond. Technol. Acad. Res. Center (STARC), Tokyo, Japan
fYear
2010
fDate
8-10 Nov. 2010
Firstpage
1
Lastpage
4
Abstract
The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.
Keywords
CMOS integrated circuits; MMIC; amplitude shift keying; error statistics; receivers; transmitters; ASK; CMOS Technology; amplitude shift keying; bit error rate; bit rate 9 Gbit/s; current 19.2 mA; current 48.2 mA; frequency 120 GHz; receiver chipset; size 65 nm; transmitter chipset; Amplitude shift keying; CMOS integrated circuits; Receivers; Semiconductor device measurement; Transceivers; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location
Beijing
Print_ISBN
978-1-4244-8300-6
Type
conf
DOI
10.1109/ASSCC.2010.5716610
Filename
5716610
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