DocumentCode :
2560188
Title :
A memory-efficient pipeline architecture for 2-D DWT of the 9/7 filter for JPEG 2000
Author :
Wu, Bing-Fei ; Lin, Chung-Fu
Author_Institution :
Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2005
fDate :
28-30 May 2005
Firstpage :
44
Lastpage :
47
Abstract :
In this paper, we propose a memory-efficient pipeline architecture which performs the one-level two-dimensional discrete wavelet transform (2D DWT) of the 9/7 filter for JPEG 2000. In general, the internal memory size of 2D architecture highly depends on the pipeline registers of 1D DWT. Based on the lifting-based DWT algorithm, the primitive data path is modified. Thus, an efficient pipeline architecture is derived to shorten the data path and decrease the internal memory size for 2D DWT. That is, for an N×M image, only 5.5N size memory is required for the 9/7 filter to perform the one-level 2D DWT decomposition with one multiplier delay (i.e. N and M indicate the height and width of an image). Based on the proposed architecture, the tradeoff between high speed and low internal memory for 2D DWT can be eased.
Keywords :
discrete wavelet transforms; filtering theory; image coding; pipeline processing; 2D DWT; 9/7 filter; JPEG 2000; lifting-based DWT; memory-efficient pipeline architecture; one-level two-dimensional discrete wavelet transform; Computer architecture; Delay effects; Discrete wavelet transforms; Filters; Hardware; Image coding; Memory architecture; Pipelines; Registers; Two dimensional displays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Cellular Neural Networks and Their Applications, 2005 9th International Workshop on
Print_ISBN :
0-7803-9185-3
Type :
conf
DOI :
10.1109/CNNA.2005.1543156
Filename :
1543156
Link To Document :
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