PRITI: Estimation of maximal currents and current derivatives in complex CMOS circuits using activities waveforms

Author

Vanoostende, Paul ; Six, Paul ; De Man, Hugo J.

Author_Institution

IMEC Lab., Leuven, Belgium

fYear

1993

fDate

22-25 Feb 1993

Firstpage

347

Lastpage

353

Abstract

Information about the maximal currents and maximal current derivatives is required to be able to estimate and limit resistive and inductive voltage drops in the on-chip power/ground wires and the bonding wires. After rigorously defining the required information in an original way, a linear-complexity pattern-independent method for its computation is proposed. The concept of an activity waveform was introduced, which allowed the translation of the overall problem into problems for the subnetworks. The landing of a subnetwork was then discussed. A comparison with the simulation of random input-patterns has shown the applicability of the proposed method for real-life VLSI building blocks of up to 15 K transistors. In addition, it has been shown that the Imax(t) and I´max(t) estimates are for these examples a factor of two to five better than the estimates used in industrial practice

Keywords

CMOS logic circuits; VLSI; circuit analysis computing; integrated circuit design; logic CAD; waveform analysis; CMOS logic; PRITI; VLSI building blocks; activities waveforms; complex CMOS circuits; current derivatives; linear-complexity pattern-independent method; logic gates; maximal currents; random input-patterns; subnetworks; CMOS logic circuits; Clocks; Energy consumption; Laboratories; Pins; Switches; Timing; Very large scale integration; Voltage; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Conference_Location

Paris

Print_ISBN

0-8186-3410-3

Type

conf

DOI

10.1109/EDAC.1993.386451

Filename

386451