Dynamically Reconfigurable Gate Array Based on Fine-Grained Switch Elements and Its CAD Environment

Dynamically programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One important issue on DPGAs is the large amount of configuration memory, which leads to area-inefficient implementation and large static power dissipation. This paper presents novel architecture of a switch block to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18 mum CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310 MHz and 272 MHz, respectively. The area of the proposed MC-FPGA is reduced to 45% of a typical MC-FPGA under a constraint of 8 contexts.