Title :
A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications
Author :
Hung, Shiang-Yu ; Yen, Shao-Wei ; Chen, Chih-Lung ; Chang, Hsie-Chia ; Jou, Shyh-Jye ; Lee, Chen-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79 Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7 Gbps/mm2 and 62.4pJ/bit, respectively.
Keywords :
CMOS integrated circuits; multiplexing equipment; parity check codes; precoding; scheduling; telecommunication network routing; 1P10M CMOS process; IEEE 802.15.3c; LDPC decoder; bit rate 5.7 Gbit/s; iteration number; multiplexers; normalized min-sum; pre-coding routing network; routing complexity; row-based layered scheduling; size 65 nm; Decoding; Hardware; Iterative decoding; Multiplexing; Routing; Scheduling;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716617
