Title :
Technology mapping algorithms for NORA dynamic logic circuits
Author :
Ortiz, Rolando Ramirez ; Lefebvre, Martin C.
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
An approach for technology mapping using cell generators and CMOS dynamic logic circuits is given. The algorithm, based on a hierarchical synchronous network graph representation, is applicable to both combinatorial and sequential circuit descriptions. The target realization is in the form of NORA pipelined data paths and is therefore most appropriate for DSP applications
Keywords :
CMOS logic circuits; combinational circuits; logic CAD; logic gates; pipeline processing; sequential circuits; CMOS dynamic logic circuits; DSP applications; NORA dynamic logic circuits; NORA pipelined data paths; algorithm; cell generators; combinatorial circuit; hierarchical synchronous network graph; sequential circuit; technology mapping; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Heuristic algorithms; Integrated circuit interconnections; Logic circuits; Logic design; Logic gates; Registers;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386457
