• DocumentCode
    2560452
  • Title

    A low-complexity heterogeneous multi-core platform for security soc

  • Author

    Huang, Wei ; Han, Jun ; Wang, Shuai ; Zeng, Xiaoyang

  • Author_Institution
    State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
  • fYear
    2010
  • fDate
    8-10 Nov. 2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents a heterogeneous multi-core SoC platform to deal with intensive cryptography algorithms in different security protocols. And several cores are integrated in the proposed Platform, which are a MlPS-like general processor (GP), a dedicated package processor (PP) for fast data package, and multiple security processors (SP) for cryptography. The low-cost dedicated SPs can execute cryptography algorithms flexibly and efficiently, and the processing performance of this platform can be enhanced easily by exploiting algorithms parallelism on multiple cores. Moreover, a test chip is implemented in SEVIC 0.13μm standard CMOS technology, and its functionality and performance are well verified. It can achieve 565Mbps, 256Mbps, 19Kbps, and 16Kbps throughput for AES(128), SHA-1, RSA(1024), ECC(p192) respectively. Comparison results shows that it also has a low-complexity hardware cost but more flexibility.
  • Keywords
    CMOS integrated circuits; cryptographic protocols; system-on-chip; MlPS; SEVIC standard CMOS technology; cryptography; dedicated package processor; heterogeneous multicore SoC platform; multiple security processors; security SoC; security protocols; size 0.13 mum; Acceleration; Algorithm design and analysis; Computer architecture; Cryptography; Protocols; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
  • Conference_Location
    Beijing
  • Print_ISBN
    978-1-4244-8300-6
  • Type

    conf

  • DOI
    10.1109/ASSCC.2010.5716621
  • Filename
    5716621