Title :
A 20MHz bandwidth continuous-time ΣΔ modulator with jitter immunity improved full-clock period SCR (FSCR) DAC and high speed DWA
Author :
Jo, Jun-Gi ; Noh, Jinho ; Yoo, Changsik
Author_Institution :
Dept. Electron. Eng., Hanyang Univ., Seoul, South Korea
Abstract :
A 20 MHz bandwidth continuous-time ΣΔ modulator with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13 μm CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) DAC for feedback. A new data weighted averaging (DWA) technique is adopted to remove the timing bottleneck at 640 MHz clock frequency. The modulator achieves 63.9 dB peak-SNDR. Dynamic range is 68 dB and decreases by only 2.3 dB when RMS clock jitter is 15 ps. The power consumption is 58 mW from a 1.2 V supply.
Keywords :
CMOS integrated circuits; continuous time systems; filters; jitter; quantisation (signal); sigma-delta modulation; switched capacitor networks; RMS clock jitter; bandwidth 20 MHz; clock jitter immunity; continuous-time ΣΔ modulator; data weighted averaging technique; frequency 640 MHz; full-clock period full clock period switched-capacitor-resistor DAC; power 58 mW; size 0.13 mum; third-order active-RC loop filter; timing bottleneck; voltage 1.2 V; word length 4 bit; Clocks; Dynamic range; Jitter; Modulation; Power capacitors; Signal to noise ratio; Thyristors;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8300-6
DOI :
10.1109/ASSCC.2010.5716627
