• DocumentCode
    2560545
  • Title

    A Scaleable DSP System for ASIP Design

  • Author

    Zhang, Yanjun ; Hu He ; Zhou, Zhixiong ; Yang, Xu ; Sun, Yihe

  • Author_Institution
    Tsinghua Univ., Beijing
  • fYear
    2006
  • fDate
    13-15 Nov. 2006
  • Firstpage
    215
  • Lastpage
    218
  • Abstract
    This paper describes a scaleable DSP architecture for ASIP design and a retargetable compiler based on ORC. By configuring this architecture, designers can easily get the ASIP for one set of applications. A DSP named THUASDSP2004 is developed manually based on this architecture and the compiler can give a satisfied result.
  • Keywords
    application specific integrated circuits; digital signal processing chips; instruction sets; integrated circuit design; logic design; ASIP design; DSP architecture; DSP system; ORC; THUASDSP2004; retargetable compiler; Application software; Application specific processors; Arithmetic; Computer architecture; Coprocessors; Costs; Digital signal processing; Hardware; Libraries; VLIW;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
  • Conference_Location
    Hangzhou
  • Print_ISBN
    0-7803-9734-7
  • Electronic_ISBN
    0-7803-97375-5
  • Type

    conf

  • DOI
    10.1109/ASSCC.2006.357889
  • Filename
    4197628
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2560545