A 1.2V, 78dB HDSP ADC with 3.1V input signal range

A low power, high resolution two-step hybrid delta-sigma/pipelined modulator (HDSP) is presented. The feedback architecture of the HDSP modulator is modified to allow higher orders of noise shaping. The pipelined quantizer is simplified. Finally, the input signal range of the HDSP modulator is extended beyond the supply voltage. The prototype chip is implemented in a 0.18/im CMOS process. With a 1.56 MHz bandwidth, 2.6 mW analog power consumption and 1.2 V analog supply voltage, the measured dynamic range and SNDR of this prototype IC are 78 dB and 75 dB.