A CMOS clock-frame regeneration chip with ECL-compatible input/output [for SONET]

Author

Chang, Z.Y. ; Delarbre, A. ; Schelfhout, K. ; Vanzieleghem, E. ; Haspeslagh, J.

Author_Institution

Alcatel Bell, Antwerp, Belgium

fYear

1993

fDate

22-25 Feb 1993

Firstpage

239

Lastpage

243

Abstract

The IC is a mixed analog/digital circuit performing the clock regeneration and frame recovery for SONET applications. The clock regeneration is realized by an analog approach, while the frame recovery is implemented using digital techniques. ECL-CMOS and CMOS-ECL converters are designed to keep the maximum peak clock jitter lower than 300 ps and the RMS jitter below 70 ps. New frame detection technique is used to relax the speed requirement on the digital part of the circuit. The chip is fabricated in a 1.2-μm-CMOS process measuring a 35-mm² silicon area. The chip is powered by as single 5-V supply and is capable of handling signals up to 180 MHz

Keywords

CMOS integrated circuits; SONET; emitter-coupled logic; mixed analogue-digital integrated circuits; synchronisation; 1.2 micron; 180 MHz; 5 V; CMOS clock-frame regeneration chip; CMOS-ECL converters; ECL-CMOS converter; ECL-compatible input/output; RMS jitter; SONET applications; frame detection technique; maximum peak clock jitter; mixed analog/digital circuit; Analog integrated circuits; Application specific integrated circuits; Area measurement; Clocks; Digital circuits; Digital integrated circuits; Jitter; SONET; Semiconductor device measurement; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on

Conference_Location

Paris

Print_ISBN

0-8186-3410-3

Type

conf

DOI

10.1109/EDAC.1993.386470

Filename

386470