Very Low-cost VLSI Implementation of AES Algorithm

This paper proposes a very low-cost VLSI implementation of AES algorithm. This design splits the 128 bit computation in every round into four 32 bit calculations and exploits 2-level pipeline to finish the process. Moreover, such improvements as module reuse and calculation order optimization, especially low-cost key expansion structure, are used to achieve high performance with very low hardware cost. Using the HHNEC 0.25 mum CMOS process, the scale of the design is about 12 K equivalent gates and its system frequency is up to 100 MHz. The throughputs of the 128 bit data encryption and decryption are as high as 256 Mbit/s.