DocumentCode
2560606
Title
Implementation alternatives of a DBNS adder
Author
Pankaala, Mikko ; Paasio, Ari ; Laiho, Mika
Author_Institution
Dept. of Inf. Technol., Turku Univ., Finland
fYear
2005
fDate
28-30 May 2005
Firstpage
138
Lastpage
141
Abstract
In this paper the implementation issues of a double-base number system (DBNS) adder are discussed. Two alternative implementation strategies, dedicated analog hardware and analog CNN processor are considered and their differences compared. The principle of including multiplication feature to the DBNS adder is discussed. Moreover, it is discussed what kind of problems arise from the finite size of the array to be used to add numbers in a DBNS form. Finally we show some simulation results.
Keywords
adders; analogue circuits; cellular neural nets; analog CNN processor; analog hardware; double-base number system adder; Arithmetic; Cellular neural networks; Computer science; Design engineering; Greedy algorithms; Hardware; Information technology; Laboratories; Microelectronics; Usability;
fLanguage
English
Publisher
ieee
Conference_Titel
Cellular Neural Networks and Their Applications, 2005 9th International Workshop on
Print_ISBN
0-7803-9185-3
Type
conf
DOI
10.1109/CNNA.2005.1543180
Filename
1543180
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