A Full-Digital Multi-Channel CMOS Capacitive Sensor

Author

Moon, B.J. ; Jung, D.-Y. ; Chung, J.-W. ; Joung, C.-Y. ; Hong, J.S. ; Lee, S.J. ; Shin, Y.H. ; Yoo, Changsik

Author_Institution

ATLab Inc. Yong-In City, Kyung-Gi-Do

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

247

Lastpage

250

Abstract

A full-digital 12-channel, 100-step capacitive sensor is described. The capacitance to be sensed forms an RC-delay line whose delay is compared with that of a reference RC-delay line. The difference of the RC delays is sensed by a simple full-digital time-to-digital converter (TDC). By compensating the parasitic capacitance at power up, the capacitive sensor implemented in a 0.35 mum standard digital CMOS technology shows 30fF sensing resolution. The capacitive sensor consumes 5 muA per channel under 3.3V supply voltage.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; capacitive sensors; compensation; delay lines; RC-delay line; current 5 muA; digital CMOS technology; full-digital CMOS capacitive sensor; full-digital time-to-digital converter; multichannel CMOS capacitive sensor; parasitic capacitance compensation; size 0.35 mum; voltage 3.3 V; CMOS technology; Capacitive sensors; Chromium; Clocks; Crosstalk; Delay lines; Dynamic voltage scaling; Integrated circuit technology; Parasitic capacitance; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357897

Filename

4197636