A cell placement procedure that utilizes circuit structural properties

A cell placement method for two-based chip layout is proposed. The proposed method utilizes the structural properties of its input circuits to guide the placement process. The algorithm first extracts the strongly connected subcircuits called cones from the circuit and then groups small cones called fragments further in order to reduce the number of extracted cones. The algorithm then performs a macrocell placement on cones which are treated as soft macros, followed by mapping the resulting macrocell placement into a cell-row placement. Finally, the algorithm applies a simulated-annealing procedure to refine the row-based placement. By utilizing the structural properties of the design, the method is fast and is able to produce a higher quality placement compared to other straightforward placement methods