Asymmetric cross-coupled sense amplifier for small-sized 0.5-V gigabit-DRAM arrays

Author

Kotabe, Akira ; Yanagawa, Yoshimitsu ; Takemura, Riichiro ; Sekiguchi, Tomonori ; Itoh, Kiyoo

Author_Institution

Central Res. Lab., Hitachi, Ltd., Tokyo, Japan

fYear

2010

fDate

8-10 Nov. 2010

Firstpage

1

Lastpage

4

Abstract

A new sense amplifier (SA) and relevant circuits were proposed for low-power, high-speed, and small-sized 0.5-V gigabit DRAM arrays. The SA, consisting of a low-V_T NMOS preamplifier and a cross-coupled high-V_T PMOS latch, achieved 46% area reduction compared to our previously proposed SA with a low-V_T CMOS preamplifier. Separation of the SA and a data-line pair, and overdrive of the latch achieved a restoring time of 13.4 ns and a sensing time of 6 ns. An adaptive leakage control of the preamplifier reduced the leakage current of the SA to 2% of that without the control.

Keywords

CMOS memory circuits; DRAM chips; leakage currents; low-power electronics; preamplifiers; adaptive leakage control; asymmetric cross-coupled sense amplifier; cross-coupled high-V_T PMOS latch; data-line pair; leakage current; low-V_T CMOS preamplifier; low-V_T NMOS preamplifier; low-power high-speed gigabit DRAM arrays; small-sized gigabit-DRAM arrays; time 13.4 ns; time 6 ns; voltage 0.5 V; CMOS integrated circuits; Latches; Leakage current; MOS devices; Preamplifiers; Sensors; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian

Conference_Location

Beijing

Print_ISBN

978-1-4244-8300-6

Type

conf

DOI

10.1109/ASSCC.2010.5716641

Filename

5716641