Title :
A 2.5GHz, 30mW, 0.03mm2, All-Digital Delay-Locked Loop
Author :
Yang, Rong-Jyi ; Liu, Shen-luan
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
A. 2.5GHz, 30mW, 0.03mm2, all-digital DLL in 0.13mum CMOS technology is presented. The lattice delay unit provides both a small delay step and a fixed intrinsic delay of two NAND gates. A modified binary search controller reduces the locking time and allows the DLL to track the PVT variations. This DLL locks in 24 cycles and has the closed-loop characteristic with pk-pk jitter of 14ps.
Keywords :
CMOS logic circuits; delay lock loops; CMOS technology; NAND gate; binary search controller; closed-loop characteristic; complementary metal-oxide-semiconductor; digital delay locked loop; frequency 2.5 GHz; intrinsic delay; lattice delay unit; locking time; power 30 mW; CMOS technology; Clocks; Counting circuits; Delay effects; Delay lines; Energy consumption; Jitter; Lattices; Logic gates; Random access memory;
Conference_Titel :
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
Conference_Location :
Hangzhou
Print_ISBN :
0-7803-9734-7
Electronic_ISBN :
0-7803-97375-5
DOI :
10.1109/ASSCC.2006.357903
