A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment

Author

Chen, You-Gang ; Wey, I-Chyn ; Wu, An-Yeu Andy

Author_Institution

Nat. Taiwan Univ., Taipei

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

295

Lastpage

298

Abstract

As the supply voltage is scaling down, both SNR and the circuit noise immunity are reduced. In this paper, we develop a new isolated noise-tolerant technique to prevent the dynamic circuit from the noise interference. As compared with the state of the art design, the noise immunity can be enhanced by 1.5X. For enhancing the noise-tolerance, we can save 81% power delay product (PDP) in severe low SNR environment. Moreover, the proposed circuit can achieve 81% and 39% energy saving as compared with the conventional domino circuit and twin-transistor design, respectively.

Keywords

integrated circuit design; integrated circuit noise; circuit noise immunity; domino circuit; energy saving; enhanced power delay product performance; isolated noise-tolerance; low SNR environment; noise immunity enhancement; noise interference; noise-tolerant dynamic circuit design; supply voltage; twin-transistor design; Circuit noise; Circuit synthesis; Crosstalk; Dynamic voltage scaling; MOS devices; Mirrors; Noise reduction; Signal to noise ratio; Threshold voltage; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357909

Filename

4197648