A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme

Author

Tanizaki, Hiroaki ; Tsuji, Takaharu ; Otani, Jun ; Yamaguchi, Yuichiro ; Murai, Yasumitsu ; Furuta, Haruo ; Ueno, Shuichi ; Oishi, Tsukasa ; Hayashikoshi, Masanori ; Hidaka, Hideto

Author_Institution

Renesas Design Corp., Itami

fYear

2006

fDate

13-15 Nov. 2006

Firstpage

303

Lastpage

306

Abstract

A high-density and high-speed memory cell named 1-transistor 4-magnetic tunnel junction (1T-4MTJ) has been proposed for magnetic random access memory (MRAM). The new 1T-4MTJ cell has been successfully demonstrated by a 1 Mb MRAM test device, using a 130 nm CMOS process. The sensing scheme of a self-reference sense amplifier with Voltage offset (SRSV) enables high-speed memory operation (access time) of tAC=56 nsec and 50 MHz@4cycle.

Keywords

CMOS memory circuits; magnetic storage; magnetic tunnelling; random-access storage; MRAM; high-density memory cell; high-speed memory cell; magnetic random access memory; magnetic tunnel junction; self-reference sense amplifier; size 130 nm; voltage offset self-reference sensing; CMOS process; CMOS technology; Costs; Flash memory cells; Magnetic tunneling; Operational amplifiers; Random access memory; Read-write memory; Testing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Conference_Location

Hangzhou

Print_ISBN

0-7803-9734-7

Electronic_ISBN

0-7803-97375-5

Type

conf

DOI

10.1109/ASSCC.2006.357911

Filename

4197650