Title :
VERTEX: VERification of Transistor-level circuits based on model EXtraction
Author :
Moondanos, J. ; Wehbeh, J.A. ; Abraham, J.A. ; Saab, D.G.
Author_Institution :
Comput. Eng. Res. Center, Univ. of Texas, Austin, TX, USA
Abstract :
VERTEX, a program that performs formal verification of synchronous sequential circuits that are characterized at the transistor-level is described. Additionally, VERTEX can compare gate-level designs or Boolean specifications against their switch-level implementations. VERTEX verifies a hardware design by employing novel techniques to extract the relevant state variables of a switch-level circuit and to compare the finite state machine descriptions of hardware designs based on formal methods for the verification of sequential circuits
Keywords :
Boolean functions; VLSI; finite state machines; formal verification; logic CAD; logic testing; sequential circuits; Boolean specifications; VERTEX; VLSI; finite state machine descriptions; formal verification; gate-level designs; hardware design; model extraction; state variables; switch-level implementations; synchronous sequential circuits; transistor-level circuits; Automata; Contracts; Formal verification; Hardware; High performance computing; Manufacturing processes; Reliability engineering; Sequential circuits; Switching circuits; Very large scale integration;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386491
