Title :
A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform
Author :
Shimano, Hiroki ; Morishita, Fukashi ; Dosaka, Katsumi ; Arimoto, Kazutami
Author_Institution :
Renesas Technol. Corp., Itami
Abstract :
The advanced-DFM RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability(@0.6 V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2 cell/bit with the complementary dynamic memory operation and has the 1 cell/bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW (sense synchronized write) peripheral circuit technologies are also adopted for the low voltage and FV controllable SoC which will be strongly required from the many kinds of applications. This RAM supports the DFM functions with both good cell/bit for advanced process technologies and the voltage scalable SoC memory platform.
Keywords :
DRAM chips; design for manufacture; system-on-chip; accelerated screening; bitline pre-charge sensing; complementary dynamic memory operation; design for manufacture; long data retention time; low power SoC platform; sense synchronized write; voltage 0.6 V; voltage scalability; voltage scalable advanced DFM RAM; Acceleration; Circuit testing; Design for manufacture; Dynamic voltage scaling; Fluctuations; Life estimation; Low voltage; Random access memory; Read-write memory; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
Conference_Location :
Hangzhou
Print_ISBN :
0-7803-9734-7
Electronic_ISBN :
0-7803-97375-5
DOI :
10.1109/ASSCC.2006.357917
