• DocumentCode
    2561139
  • Title

    A 6-bit 1.6 GS/s Flash ADC in 0.18-μm CMOS with Reversed-Reference Dummy

  • Author

    Hung, Chien-Kai ; Shiu, Jian-Feng ; Chen, I-Ching ; Chen, Hsin-Shu

  • Author_Institution
    Nat. Taiwan Univ., Taipei
  • fYear
    2006
  • fDate
    13-15 Nov. 2006
  • Firstpage
    335
  • Lastpage
    338
  • Abstract
    A 6-bit 1.6 GS/s CMOS flash ADC using reversed-reference dummy method is demonstrated in a standard 0.18-μm CMOS process. The proposed method improves linearity error at the boundary of offset averaging networks. The prototype circuit exhibits an INL of +0.32/-0.28 LSB and a DNL of +0.28/-0.28 LSB. The SNDR and SFDR achieve 32 and 44 dB at 1.6 GS/s for Nyquist input frequency. The ADC consumes 350 mW at 1.8 V supply and occupies an active chip area of 0.46 mm2.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; CMOS; DNL; INL; LSB; Nyquist input frequency; SFDR; SNDR; bit rate 1.6 Gbit/s; flash ADC; offset averaging networks; power 350 mW; reversed-reference dummy; voltage 1.8 V; Analog-digital conversion; CMOS process; CMOS technology; Circuits; Frequency; Linearity; Low voltage; Modems; Preamplifiers; Prototypes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
  • Conference_Location
    Hangzhou
  • Print_ISBN
    0-7803-9734-7
  • Electronic_ISBN
    0-7803-97375-5
  • Type

    conf

  • DOI
    10.1109/ASSCC.2006.357919
  • Filename
    4197658
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2561139