An Undersampling 10-bit 30.4-MSample/s Pipelined ADC

A 3.3V 10bit 30.4-MS/s pipelined analog-to-digital converter (ADC) is presented. The application of undersampling input is considered and analyzed in particular. The flip-around S/H circuit is introduced to reduce the requirement of amplifier´s performance and achieve low noise. The gate-voltage bootstrapped switch is used to allow a wideband input signal with excellent linearity. The gain-boost telescopic cascode amplifier is adopted to consume lower power The ADC achieved a signal-to-noise-and-distortion ratio (SNDR) of 56.5dB (9.1ENOB) for an input of 30 MHz at full speed of 30.4 MHz, consuming only 52 mW. The ADC is implemented in a 0.35mum CMOS technology and occupies an area of 1.47mm².