Title :
An integrated approach to pin assignment and global routing for VLSI building-block layout
Author :
Koide, Tetsushi ; Wakabayashi, Shin´ichi ; Yoshida, Noriyoshi
Author_Institution :
Fac. of Eng., Hiroshima Univ., Kagamiyama, Higashi-Hiroshima, Japan
Abstract :
An efficient algorithm integrating global routing, pin assignment, block reshaping and positioning, which is based on a rip-up and reroute and the simulated evolution technique, is presented. Experimental results show that the proposed algorithm achieves up to 10.5% reduction of chip area and up to 34.6% reduction of total wire length compared with previous methods
Keywords :
VLSI; circuit layout CAD; integrated circuit layout; network routing; VLSI building-block layout; algorithm; block reshaping; global routing; integrated approach; pin assignment; positioning; rip-up and reroute; simulated evolution technique; Algorithm design and analysis; Design engineering; Heuristic algorithms; Partitioning algorithms; Pins; Routing; Shape; Terminology; Very large scale integration; Wires;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386506
