A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter

This paper presents the design of a phase-locked loop (PLL) based clock and data recovery (CDR) circuit that meets fast locking and low jitter. We reduce the locking time of a CDR circuit using a new autonomously reconfigurable charge pump and loop filter in a 1.25 Gb/s CDR circuit. An experimental prototype was implemented in a 0.18 mum standard CMOS technology. A receiver that incorporates our CDR circuit has an active area of 380 mum times 350 mum.