Title :
A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter
Author :
Woo, Jong-Kwan ; Lee, Hyunjoong ; Shin, Woo-Yeol ; Song, Heesoo ; Jeong, Deog-Kyoon ; Kim, Suhwan
Author_Institution :
Seoul Nat. Univ., Seoul
Abstract :
This paper presents the design of a phase-locked loop (PLL) based clock and data recovery (CDR) circuit that meets fast locking and low jitter. We reduce the locking time of a CDR circuit using a new autonomously reconfigurable charge pump and loop filter in a 1.25 Gb/s CDR circuit. An experimental prototype was implemented in a 0.18 mum standard CMOS technology. A receiver that incorporates our CDR circuit has an active area of 380 mum times 350 mum.
Keywords :
CMOS integrated circuits; filters; jitter; phase locked loops; CMOS technology; PLL; autonomously reconfigurable charge pump; clock and data recovery circuit; fast-locking CDR circuit; loop filter; phase-locked loop; reconfigurable charge pump; Bandwidth; CMOS technology; Charge pumps; Circuits; Clocks; Detectors; Filters; Frequency; Jitter; Phase locked loops;
Conference_Titel :
Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian
Conference_Location :
Hangzhou
Print_ISBN :
0-7803-9734-7
Electronic_ISBN :
0-7803-97375-5
DOI :
10.1109/ASSCC.2006.357938
