Title :
Development of parallelism for circuit simulation by tearing
Author :
Onozuka, H. ; Kanoh, M. ; Mizuta, C. ; Nakata, T. ; Tanabe, N.
Author_Institution :
ULSI Syst. Dev. Lab., NEC Corp., Kawasaki, Kanagawa, Japan
Abstract :
A hierarchical clustering with min-cut exchange method for parallel circuit simulation is presented. Partitioning into subcircuits is near optimum in terms of distribution of computational cost and does not sacrifice the sparsity of the entire matrix. In order to compute the arising dense interconnection matrix in parallel, multilevel and distributed row-base dissection algorithms are used. A processing speed up of 28 with 64 processors was achieved in large scale DRAM simulations
Keywords :
DRAM chips; circuit analysis computing; circuit layout CAD; integrated circuit layout; logic partitioning; multistage interconnection networks; parallel algorithms; circuit simulation; dense interconnection matrix; distributed row-base dissection algorithms; distribution of computational cost; hierarchical clustering; large scale DRAM simulations; min-cut exchange method; multilevel algorithms; parallelism; partitioning into subcircuits; tearing; Circuit simulation; Clustering algorithms; Computational efficiency; Concurrent computing; Distributed computing; Integrated circuit interconnections; Large-scale systems; Parallel processing; Partitioning algorithms; Random access memory;
Conference_Titel :
Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on
Conference_Location :
Paris
Print_ISBN :
0-8186-3410-3
DOI :
10.1109/EDAC.1993.386508
