Design and implementation of a multiprocessor with hypercube interconnection network

Author

Nagata, Motoyasu ; Fukuda, Shuji ; Kihara, Ken-ichi

Author_Institution

Osaka Electro-Commun. Univ., Japan

fYear

1989

fDate

6-10 Nov 1989

Firstpage

775

Abstract

The authors present the design and implementation of a multiprocessor with a hypercube interconnection network. The hardware configuration of the hypercube multiprocessor is realized by using 16 processing elements (PEs) with a single CPU and five parallel interfaces per PE. Four programmable parallel interfaces (PPI) are interconnected with four adjacent PEs in a hypercube manner, and the other PPI is directly connected to the control computer. The software structure is also presented, focusing on the communication mechanism between adjacent PEs of the hypercube multiprocessor and communication between the PE and the control computer. Furthermore, the implemented graphic display control and its interface are briefly described from the viewpoint of hardware. The designed system has wide applicability in parallel computation with load balancing among PEs of the hypercube multiprocessor

Keywords

computer graphic equipment; multiprocessing systems; parallel machines; parallel programming; CPU; communication mechanism; control computer; design; graphic display control; hardware; hypercube interconnection network; implementation; load balancing; multiprocessor; parallel interfaces; parallel processing; processing elements; software structure; Communication system control; Computer displays; Computer graphics; Computer interfaces; Concurrent computing; Hardware; Hypercubes; Load management; Multiprocessor interconnection networks; Software;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics Society, 1989. IECON '89., 15th Annual Conference of IEEE

Conference_Location

Philadelphia, PA

Type

conf

DOI

10.1109/IECON.1989.69727

Filename

69727