DocumentCode :
2561741
Title :
A VLSI architecture for computing the tree-to-tree distance
Author :
Sastry, Raghu ; Ranganathan, N.
Author_Institution :
HAL Comput. Syst., Campbell, CA, USA
fYear :
1995
fDate :
1995
Firstpage :
330
Lastpage :
339
Abstract :
The distance between two labeled ordered trees, α and β is the minimum cost sequence of editing operations (insertions, deletions and substitutions, needed to transform or into β such that the predecessor-descendant relation between nodes and the ordering of nodes is not changed). Approximate tree matching has applications in genetic sequence comparison, scene analysis, error recovery and correction in programming languages, and cluster analysis. Edit distance determination is a computationally intensive task, and the design of special purpose hardware could result in a significant speed up. This paper describes in detail a VLSI architecture for computing the edit distance between arbitrary ordered trees, based on a parallel, systolic realization of the dynamic programming algorithm proposed by S.Y. Lu (1979). This architecture represents a significant improvement over that described by Sastry and Ranganathan (1994), which restricted the type of trees that could be processed by it. Two partitioning strategies to process trees of arbitrary sizes and structures on a fixed size implementation in multiple passes are proposed and analyzed
Keywords :
VLSI; dynamic programming; parallel algorithms; pattern matching; systolic arrays; trees (mathematics); VLSI architecture; approximate tree matching; cluster analysis; deletions; dynamic programming algorithm; edit distance determination; editing operations; error recovery; fixed size implementation; genetic sequence comparison; insertions; labeled ordered trees; minimum cost sequence; parallel systolic realization; partitioning strategies; predecessor-descendant relation; programming languages; scene analysis; substitutions; tree-to-tree distance computation; Computer architecture; Computer languages; Concurrent computing; Costs; Dynamic programming; Error correction; Genetics; Hardware; Image analysis; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Performance Computer Architecture, 1995. Proceedings., First IEEE Symposium on
Conference_Location :
Raleigh, NC
Print_ISBN :
0-8186-6445-2
Type :
conf
DOI :
10.1109/HPCA.1995.386530
Filename :
386530
Link To Document :
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