Correlation of device performance to die-level stress variations

Advanced technology nodes are increasingly dependent on strain engineering to achieve the performance targets. However, processes throughout device fabrication have the potential to inadvertently relax or modify the stress. The relative importance of die-level stress variations induced across multiple processes effect the device performance is examined in this study. Specifically, CGS stress metrology is used to characterize stresses induced across numerous steps in a 65 nm process to explore the correlation between die-level stresses and device performance. It is demonstrated that stress variations may account for as much as 49% of the device performance variance.