The impact of junction depth on vertical sidewall MOSFETs with embedded gate

Author

Kuo, Chih-Hao ; Lin, Jyi-Tsong ; Lee, Tai-Yi ; Eng, Yi-Chuen ; Chang, Tzu-Feng ; Lin, Po-Hsieh ; Chen, Hsuan-Hsu ; Sun, Chih-Hung ; Chiu, Hsien-Nan

Author_Institution

Dept. of EE, Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2009

fDate

11-12 June 2009

Firstpage

51

Lastpage

53

Abstract

In this work, we present a novel vertical MOSFET with embedded gate structure and try to overcome the challenges mentioned above by modifying the junction depth. Therefore, four types of vertical sidewall MOSFETs with embedded gate (EVGMOS) are also demonstrated and called the EVGMOS having lightly-doped drain (LDD) w/o or w/ 2.5 nm Si etching after gate formation and non-LDD w/o or w/ 2.5 nm Si etching after gate formation for comparison. The preliminary results are shown using TCAD simulations.

Keywords

MOSFET; elemental semiconductors; etching; semiconductor junctions; silicon; Si; TCAD simulations; embedded gate structure; gate formation; junction depth; lightly-doped drain; silicon etching; size 2.5 nm; vertical sidewall MOSFET; Controllability; Costs; Etching; FETs; MOS devices; MOSFETs; Parasitic capacitance; Silicon; Sun; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2009. IWJT 2009. International Workshop on

Conference_Location

Kyoto

Print_ISBN

978-1-4244-3319-3

Electronic_ISBN

978-1-4244-3320-9

Type

conf

DOI

10.1109/IWJT.2009.5166218

Filename

5166218