• DocumentCode
    2562184
  • Title

    Creating a wider bus using caching techniques

  • Author

    Citron, Daniel ; Rudolph, Larry

  • Author_Institution
    Inst. of Comput. Sci., Hebrew Univ., Jerusalem, Israel
  • fYear
    1995
  • fDate
    1995
  • Firstpage
    90
  • Lastpage
    99
  • Abstract
    The effective bandwidth of a bus and external communication ports can be increased by using a variant of data compression techniques that compacts words instead of data streams. The compaction is performed by caching the high order bits into a table and sending the index into the table along with the low order bits. A coherent table at the receiving end expands the word into it original form. Compaction/expansion units can be placed between processor and memory, between processor and local bus, and between devices that access the system bus. Simulations have shown that over 90% of all informative transferred can be sent in a single cycle when using a 32 bit processor connected by a 16 bit wide bus to a 32 bit memory module. This is for all forms of data, address, data, and instructions, and when a cache-based processor is used
  • Keywords
    cache storage; data compression; system buses; 16 bit; 32 bit; cache-based processor; caching techniques; data compression techniques; effective bandwidth; external communication ports; memory module; Bandwidth; Compaction; Computer aided instruction; Computer science; Data compression; Degradation; Microprocessors; Pins; System buses; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computer Architecture, 1995. Proceedings., First IEEE Symposium on
  • Conference_Location
    Raleigh, NC
  • Print_ISBN
    0-8186-6445-2
  • Type

    conf

  • DOI
    10.1109/HPCA.1995.386552
  • Filename
    386552