Title :
An Improved Algorithm For Minimum-area Retiming
Author :
Maheshwari, Naresh ; Sapatnekar, Sachin S.
Author_Institution :
Department of Electrical & Computer Engineering Iowa State University
Keywords :
Clocks; Delay; Design automation; Flip-flops; Linear programming; Logic circuits; Logic gates; Permission; Timing; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-7803-4093-0
DOI :
10.1109/DAC.1997.597107
